1. Field of the Invention
This invention relates to a method of semiconductor fabrication, and more particularly to a method for fabricating an isolating structure in fabrication of an integrated circuit (IC) device.
2. Description of Related Art
The purpose of an isolation region in an IC device is to prevent a carrier from drifting between two adjacent device elements through a semiconductor substrate to cause a leakage. For example, carriers drift between two adjacent transistors through their substrate. Conventionally, isolation regions are formed between field effect transistors (FETs) in an IC device, such as a dynamic random access memory (DRAM) device, to prevent a current leakage from occurring. The isolation region usually includes a thick field oxide (FOX) layer formed directly on the substrate. For example, a local oxidation (LOCOS) process is a typical isolation process widely used for isolating a metal oxide semiconductor (MOS) transistor. The LOCOS technology has been well developed so that it can effectively isolate the MOS transistor or other kinds of device elements with a good reliability of performance. The fabrication cost thereby is reduced. However, the LOCOS technology still has some problems, for example, tensile stress related problems and an occurrence of bird's peak on the edge of an isolation structure, which is often seen in a FOX layer formed through the LOCOS technology.
As the device dimension is reduced in the IC device, the dimensions of active regions and the space between active regions are accordingly reduced as well. It causes to be thinner for a FOX layer formed by the LOCOS technology in this narrow space between active regions. The FOX layer thereby cannot effectively perform its isolation purpose. Moreover, during forming the FOX layer, a bird's peak occurs at the edge of the active region. Because the FOX layer and the active region include different materials, a gate oxide layer formed over the active region has a smaller thickness at the bird's peak edge due to the tensile stress. A current leakage thereby occurs on the gate oxide layer.
Shallow trench isolation (STI) is another widely used technology for isolating device elements. The STI process usually uses a silicon nitride layer as a mask to form a trench on the substrate by anisotropic etching. Then the trench is filled with an oxide material serving as an isolating structure, which has a top surface as high as the substrate surface. A MOS transistor is formed, for example, on the substrate between isolation structures at an active region. The MOS transistor over the active region includes two interchangeable source/drain regions on the substrate, a gate oxide layer, and a polysilicon gate over the gate oxide layer between the interchangeable source/drain regions. A channel region under the gate on the substrate is also formed. The depth of the STI structure determines the isolating effect. The STI structure can therefore be applied in a smaller device dimension.
FIGS. 1A-1D are cross-sectional views schematically illustrating a fabrication flow of a STI structure. In FIG. 1A, a pad oxide layer 11 and a silicon nitride layer 12 are sequentially formed over a semiconductor substrate 10. Then a photoresist layer 14 with a trench pattern is formed over the silicon nitride layer 12 by a photolithography process. Then, a trench 16 is formed by performing an anisotropic etching on the substrate 10 according to the trench pattern on the photoresist layer 14.
In FIG. 1B, after removing the photoresist layer 14, a thermal oxide layer 18 with a thickness of about between 300 .ANG. and 500 .ANG. is formed over the trench surface by thermal oxidation at a temperature of about between 900.degree. C. and 1100.degree. C. An oxide layer 20 is formed over the substrate 10 by, for example, atmospheric chemical vapor deposition (APCVD) with a reaction gas of tetra-ethyl-ortho-silicate (TEOS). The TEOS oxide layer 20 needs a densification process at a temperature of about between 900.degree. C. and 1100.degree. C. for about 10 to 30 minutes. In FIG. 1C, after the densification process, a chemical mechanical polishing (CMP) process is performed to polish the TEOS oxide layer 20 above the silicon nitride 12, which serves as a polishing stop layer. The residual TEOS oxide layer fills the trench 16 as an oxide plug 20a. The oxide plug 20a is used for isolation.
In FIG. 1D, the silicon nitride layer 12 and the oxide layer 11 are removed to expose the substrate 10. The top portion of the oxide plug 20a is also removed and becomes an oxide plug 20b. Next, a gate oxide layer (not shown) is formed by dry oxidation at an active region on the substrate 10, in which the active region is the region other than the oxide plug 20b. Then a polysilicon layer (not shown) is formed over the gate oxide layer by chemical vapor deposition (CVD). The polysilicon layer is doped by, for example, ion implantation and annealing or directly doped with dopant during CVD process. Then a gate structure including an oxide layer 22 and a doped polysilicon layer 24 as a gate are formed by photolithography and etching.
This conventional method described above needs the CMP process to remove the TEOS oxide layer 20. It causes a higher fabrication cost due to the CMP process itself and a low fabrication efficiency because the CMP process can polish only one wafer in each time.